1. Field of the Invention
The present invention relates to memories formed in integrated circuits and provided with redundancy elements.
The present invention more specifically relates to integrated circuit memories formed of several arrays provided with amplifiers for reading the memory cells of each network and sharing common input/output circuits.
2. Discussion of the Related Art
The function of redundancy elements is to increase the manufacturing output of integrated circuit memories by functionally replacing a defective element with a redundancy element. An integrated circuit memory is generally made in the form of one of several arrays of cells for storing an information bit. The redundancy element generally is a row or a column of additional cells.
To simplify the present description, reference will be made, by an arbitrary convention, to a memory in which the redundancy element(s) are columns. However the present invention also applies to a memory in which the redundancy element(s) are rows.
FIG. 1 very schematically shows a conventional example of a memory circuit architecture to which the present invention applies.
In the example of FIG. 1, the memory is divided into p banks or arrays Bl, Bk, Bp−1, Bp of memory cells, each including a row of sense amplifiers SAl, SAp−1, SAp. Each memory cell bank includes a number of columns generally corresponding to number n of bits in a memory word, plus at least one redundancy column intended for replacing a column in which a defective element is present. In the example of FIG. 1, the rows of sense amplifiers are arranged between two half-banks of memory cells. This is an example and the present invention also applies to the case where the sense amplifier rows are arranged at the ends of the memory cell banks.
The amplifiers of the different banks are connected, per column, by means of input/output lines IOL intended for conveying the signals from the sense amplifiers to input/output elements 10 of the memory. These elements are generally called input/output buffers (I/O buffers) and are by a number n corresponding to the number of columns in the memory (with no redundancy column). To organize the redundancy, the input/output lines are interrupted between row 10 and first bank Bl by a row 5 of switches or the like. Rank 5 includes means enabling, in the presence of a defective memory element in the column corresponding to a buffer, successively shifting the memory cell column used in relation with this input/output buffer and the following ones. In the left-hand portion of FIG. 1, the presence of a defect di has been assumed in a column i. The two outputs (direct and complementary) of the input/output buffer on the side of the memory cells of column i−1 are connected, by switching means 5, to line IOLi−1. To simplify, reference is made to a line IOL although two conductors are actually involved. The outputs on the memory side of the input/output buffer associated with column i are however connected, by means 5, to line IOLi+1. The shifting performed by circuit 5 continues until the last input/output buffer n, which is connected to line IOLn+1 corresponding to the redundancy column. Row 10 of input/output buffers includes n buffers while the memory cell arrays, as well as the sense amplifier rows, include n+1 columns.
In a memory architecture such as illustrated in FIG. 1, the redundancy is used not only to isolate a column of defective memory elements but also, given the interleaving of the sense amplifiers between the arrays, to isolate the amplifier from the defective column. This is a substantial improvement with respect to still prior redundancy systems where the sense amplifiers could not be repaired by redundancy elements.
The constraint of such a repair is to necessitate a disabling of the sense amplifiers of the defective column, for example, by cutting off their biasing. This is necessary since the most frequent problem of sense amplifiers is a short-circuit and that it is then necessary to turn off their power supply. Further, it is not known to isolate, by testing methods, whether the defect comes from an amplifier in the column or from a memory cell in this column.
To cut off the power supply of the amplifier of a defective column, a column conductor CTRL associated with each memory column is used, as illustrated by the right-hand portion of FIG. 1 detailing a column 12. This conductor is used to convey a signal for controlling the supply of the column amplifiers from row 5 of switch elements. Row 5 then integrates not only the elements necessary to organize the redundancy, but also to control the deactivation of the supply of an amplifier column.
In the forming of a memory circuit, the arrangement of the different components with respect to one another is linked to the necessary interconnections between these components to minimize the number of metallization levels of the integrated circuits. For example, and as illustrated in the right-hand portion of FIG. 1, the input/output lines (IOLi), formed of a direct conductor IOLd and of a complementary conductor IOLc, are formed in the same metallization level as conductors CTRL for disabling the different amplifiers. The connections between the memory cells and the sense amplifiers (the bit lines not shown) are formed in an underlying metallization level with which conductors IOLd, IOLc, and CTRL communicate by vias v at the level of each amplifier of a column.
As appears from the discussion of FIG. 1, the existence of a defect in a memory array disables the use of the corresponding column in all the memory arrays sharing the input/output buffer.
Such a redundancy organization is well known and described, for example, in U.S. Pat. No. 5,506,807, which is incorporated herein by reference.
In the row direction, a memory further includes row-decoding elements associated with control elements. Physically, all these elements are, in the memory plane, generally gathered in a strip 15 located on one side of the arrays. Most often, an integrated memory circuit further includes column decoders (not shown) used to select a set of arrays illustrated in FIG. 1 by a succession of sets placed side by side.
A redundancy technique such as illustrated in FIG. 1 provides satisfactory results as long as the memory size remains relatively small. In practice, between 2 and 6 redundancy columns are provided. As a result, the number of columns likely to be repaired is limited in the same proportions. Now, the more the memory size increases, that is, the more the number of arrays sharing same input/output buffers increases, the higher the number of defects to be repaired statistically is. This thus poses the problem of having, either to unreasonably increase the number of redundancy columns, or to restrict the number of memory cell arrays sharing the same input/output buffers. Now, the input/output buffers are among the most bulky elements of an integrated circuit memory, and it is desirable to share them as much as possible.